One of the most important considerations for handling network traffic is packet throughput (i.e., bandwidth). Network processors and the like are designed to efficiently process very large numbers of packets per second. In order to process a packet, the network processor (and/or switch equipment employing the network processor) needs to extract data from the packet header indicating the destination of the packet, class of service, etc., store the payload data in memory, perform various overhead functions, etc.
Under a typical packet processing scheme, a packet (or the packet's payload) is stored in a “packet” buffer, while “metadata” used for processing the packet is stored elsewhere in some type of metadata buffer. Whenever a packet-processing operation needs to access the packet or metadata, a memory access operation is performed. Each memory access operation adds to the overall packet-processing latency.
Ideally, all memory accesses would be via the fastest scheme possible. For example, modern on-chip (i.e., on the processor die) static random access memory (SRAM) provides access speeds of 10 nanoseconds or less. However, this type of memory is very expensive (in terms of chip real estate and chip yield), so the amount of on-chip SRAM memory provided with a processor is usually very small. Typical modern network processors employ a small amount of on-chip SRAM for scratch memory and the like.
The next fastest type of memory is off-chip SRAM. Since this memory is off-chip, it is slower to access (than on-chip memory), since it must be accessed via an interface between the network processor and the SRAM store. Thus, a special memory bus is required for fast access. In some designs, a dedicated back-side bus (BSB) is employed for this purpose. Off-chip SRAM is generally used by modern network processors for storing and processing packet metadata, along with storing other temporal processing-related information.
Typically, various types of off-chip dynamic RAM (DRAM) are employed for use as “bulk” memory. Dynamic RAM is slower than static RAM (due to physical differences in the design and operation of DRAM and SRAM cells), and must be refreshed every few clock cycles, taking up additional overhead. As before, since it is off-chip, it also requires a special bus to access it. In most of today's network processor designs, DRAM memory stores with enhanced performance are employed, including RDRAM (Rambus DRAM) or DDR DRAM (double data rate), RLDRAM (reduced latency RAM) etc. via dedicated signals. As used herein, a memory store comprises one or more memory storage devices having memory spaces that are managed as a common memory space.
In consideration of the foregoing characteristics of the various types of memory, network processors are configured to store packet data in slower bulk memory (e.g., DRAM), while storing metadata in faster memory comprising SRAM. Accordingly, modern network processors usually provide built-in hardware facilities for allocating and managing metadata buffers and access to those buffers in an SRAM store coupled to the network processor. Furthermore, software libraries have been developed to support packet-processing via microengines running on such network processors, wherein the libraries include packet-processing code (i.e., functions) that is configured to access metadata via the built-in hardware facilities.